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Selected Topics in Electronics and Systems - Vol. 5
HIGH PERFORMANCE DESIGN AUTOMATION FOR MULTI-CHIP MODULES AND PACKAGES
edited by J-D Cho (Sung Kyun Kwan Univ.) & P D Franzon (North Carolina State Univ.)
Today's electronics industry requires new design automation methodologies that allow designers to incorporate high performance integrated circuits into smaller packaging. The aim of this book is to present current and future techniques and algorithms of high performance multichip modules (MCMs) and other packaging methodologies. Innovative technical papers in this book cover design optimization and physical partitioning; global routing/multi-layer assignment; timing-driven interconnection design (timing models, clock and power design); crosstalk, reflection, and simultaneous switching noise minimization; yield optimization; defect area minimization; low-power physical layout; and design methodologies. Two tutorial reviews review some of the most significant algorithms previously developed for the placement/partitioning, and signal integrity issues, respectively. The remaining articles review the trend of prime design automation algorithms to solve the above eight problems which arise in MCMs and other packages.
Contents:
- Physical Design Optimization for MCMs: An
Overview of Placement and Routing Algorithms for Multi-Chip Modules (S Chattopadhyay et al.)
- Early Feasibility and Cost Assessment for Multichip Module Technologies (R C Carden IV & C-K Cheng)
- Pin Redistribution Problem for Multi-Chip Modules: Algorithms and Complexity (D Chang & T F Gonzalez)
- Layer Assignment for High-Speed MCM Packaging (K-Y Chao & D F Wong)
- 63-Layer TCM Wiring with Three-Dimensional Crosstalk Constraints (H H Chen & C K Wong)
- A New Layout Design System for Multichip Modules (B M Riess & A A Schoene)
- Other MCM and Package Design Optimizations: An Overview of Techniques for Partitioning Multichip Modules (S Raman & L M Patnaik)
- Interconnect Design and Synthesis in High Speed Printed Circuit Boards and Multi-Chip Modules (R Goyal)
- Board Level Partitioning for Improved Partial Scan (S Tragoudas)
- Optimal Algorithms for Substrate Testing in Multi-Chip Modules (A B Kahng et al.)
- Three-Dimensional Packaging for High-Performance Interconnect in Large-Scale VKSI Systems (A DeHon et al.)
- Area Efficient Layout of Balanced Hypercubes (K Huang & J Wu)
- Simultaneous Switching Noise Analysis of a 16 Mb ´ 9 DRAM SIMM Memory Module (J-H Park et al.)
Readership: Computer scientists, electrical and electronic engineers.
| 264pp |
Pub. date: Jun 1996 |
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