by Weidong Liu (Synopsys, USA) & Chenming Hu (University of California, Berkeley, USA)

Table of Contents (56k)
Foreword (50k)
Preface (44k)
Chapter 1: BSIM and IC Simulation (92k)

About Weidong Liu

About Chenming Hu

This book presents the art of advanced MOSFET modeling for integrated circuit simulation and design. It provides the essential mathematical and physical analyses of all the electrical, mechanical and thermal effects in MOS transistors relevant to the operation of integrated circuits. Particular emphasis is placed on how the BSIM model evolved into the first ever industry standard SPICE MOSFET model for circuit simulation and CMOS technology development.

The discussion covers the theory and methodology of how a MOSFET model, or semiconductor device models in general, can be implemented to be robust and efficient, turning device physics theory into a production-worthy SPICE simulation model.

Special attention is paid to MOSFET characterization and model parameter extraction methodologies, making the book particularly useful for those interested or already engaged in work in the areas of semiconductor devices, compact modeling for SPICE simulation, and integrated circuit design.

• BSIM and IC Simulation:
  • Circuit Simulation and Compact Models
  • BSIM — The Beginning
  • BSIM3 — A Compact Model Based on New MOSFET Physics
  • BSIM3v3 — World's First MOSFET Standard Model
  • BSIM4 — Aimed for 130nm Down to 20nm Nodes
  • BSIM SOI
  • Impact of BSIM
  • Looking Towards the Future — The Multi-Gate MOSFET Model
  • The Intent of This Book
• Fundamental MOSFET Physical Effects and Their Models for BSIM4:
  • Introduction and Chapter Objectives
  • Gate and Channel Geometries and Materials
  • Temperature-Dependence Model Options
  • Threshold Voltage
  • Poly-Silicon Gate Depletion
  • Bulk-Charge Effects
  • LDD Resistances
  • Finite Charge Thickness
  • Effective Mobility
  • Layout-Dependent Effects: Mechanical Stress and Proximity Effects
  • Chapter Summary
  • Parameter Table
• Channel DC Current and Output Resistance:
  • Introduction and Chapter Objectives
  • Channel Current Theory
  • Single Continuous Channel Charge Model
  • Channel Current in Subthreshold and Linear Operations
  • Velocity Saturation and Velocity Overshoot
  • Output Resistance in Saturation Region
  • Source-End Velocity Limit
  • Chapter Summary
  • Parameter Table
• Gate Direct-Tunneling and Body Currents:
  • Introduction and Chapter Objectives
  • Gate Direct-Tunneling Current Theory and Model
  • Body Currents
  • Summary of BSIM4 Branch and Terminal DC Currents
  • Chapter Summary
  • Parameter Table
• Charge and Capacitance Models:
  • Introduction and Chapter Objectives
  • MOSFET Capacitance Theory
  • Intrinsic Charge and Capacitance Models
  • Fringing and Overlap Capacitances
  • Chapter Summary
  • Parameter Table
• Non-Quasi-Static and Parasitic Gate and Body Resistances:
  • Introduction and Chapter Objectives
  • Gate Electrode Resistance
  • Gate Intrinsic-Input Resistance for Non-Quasi-Static Modeling
  • Charge-Deficit Transient and AC NQS Models
  • Body Resistance Network
  • Chapter Summary
  • Parameter Table
• Noise Models:
  • Introduction and Chapter Objectives
  • Noise Representations and Parameters
  • BSIM4 Flicker Noise Models
  • BSIM4 Channel Thermal Noise Models
  • Other Noise Sources
  • Chapter Summary
  • Parameter Table
• Source and Drain Parasitics: Layout-Dependence Model:
  • Introduction and Chapter Objectives
  • Connections of a Multi-Transistor Stack
  • Source and Drain of a Transistor With Multiple Gate Fingers
  • GEOMOD: The End-Source and End-Drain of a Multi-Finger Transistor
  • Source and Drain Area and Perimeter Calculation
  • Saturation Junction Leakage Current and Zero-Bias Capacitance Models
  • Source and Drain Contact Scenarios and Diffusion Resistances
  • RGEOMOD: Selecting A Source and Drain Contact Scenario for GEOMOD
  • Chapter Summary
  • Parameter Table
• Junction Diode IV and CV Models:
  • Introduction and Chapter Objectives
  • Physical Mechanisms of Diode DC Currents
  • BSIM4 Diode DC IV Model [4]
  • BSIM4 Junction Leakage Due to Trap-Assisted Tunneling [4]
  • BSIM4 Diode Charge and Capacitance [4]
  • Diode Temperature-Dependence Model [4]
  • Chapter Summary
  • Parameter Table
• SPICE Implementation Example: The Methodology with BSIM4 Transient NQS:
  • Introduction and Chapter Objectives
  • Review of the Charge-Deficit Transient NQS Model
  • Time Discretization, Equation Linearization and Matrix Stamping
  • Composite Stamps for Transient NQS Model
  • Bypass
  • Convergence Checking
  • Chapter Summary
• Multi-Gate Transistor Model:
  • Introduction and Chapter Objectives
  • Advantages of FinFETs Over Planar CMOS
  • BSIM-CMG
  • Model Validation
  • Chapter Summary